The number of transistors that can be formed on an integrated circuit chip continues to increase with the trend toward higher integration. Accordingly, integrated circuits become more sophisticated and demand an increased number of input and output I/O terminals or leads. Therefore, the number of bonding pads placed at the edges of the chip die likewise increases, which places constraints on the chip packaging.
In an integrated circuit die, the bonding pads are commonly placed at the perimeter of the chip. The die is mounted to a lead frame or package substrate, which in turn contains a number of pins or leads for distributing the signals from the bonding pads of the die to a circuit panel to which the chip package is mounted. The lead frame or package substrate includes a number of leads that are generally aligned with the bonding pads of the chip die. The leads are coupled to the bonding pads by bonding wires.
FIG. 1 is a plan view of a conventional bonding configuration. Chip die 1 includes a plurality of bonding pads 3 along an edge of the die 1. The bonding pads 1 are coupled to a plurality of corresponding leads 5 of a lead frame by bonding wires 7 at bonding regions 9 of the lead frame. The bonding regions 9 are also commonly referred to as “inner lead tips”, for lead frames, or “bonding fingers”, for package substrate configurations. The leads 5 are larger in size than the corresponding bonding pads 3. The angle at which the bonding wire 7 lies relative to an axis that is normal to the edge of the die 1 passing through the corresponding pad 3 is referred to as a “bonding angle”. Bonding wires 7 coupled to bonding pads 3 in a central region of the edge of the chip are spaced apart by a distance S2, while bonding wires 7 coupled to bonding pads 3 in a corner region of the edge of the chip are spaced apart by a distance S1. The distance S1 between the bonding wires in the corner regions of the die is less than the distance S2 between the bonding wires in the central region of the die because of the increased bonding angle of the wires in the corner regions owing to the larger size of the leads 5. With the reduced distance S1 between wires in the corner regions, there is an increased likelihood of shorting between bonding wires in the corner regions during the final stages of chip packaging, a costly time at which to introduce defects in the fabrication process since manufacture of the chip is nearly completed at that time.
To overcome wire-to-wire shorting in the corner regions, the spacing between bonding pads 3 is made to increase from the central regions of the die to the corner regions. FIG. 2 is a plan view of a conventional bonding configuration in which the spacing, or “pitch”, between bonding pads 3 is increased in this manner. This increase in pitch is generally referred to as the “corner rule”. Using the corner rule, it can be seen in FIG. 2 that the pitch P1 between bonding pads 3 in the central region is less than the pitch P2 between bonding pads 3 in an intermediate region, which, in turn, is less than the pitch P3 between bonding pads 3 in the corner region (P1<P2<P3). The corner rule applies to bonding pads both along vertical and horizontal edges of the die and in all quadrants of the die. By increasing the pitch between bonding pads in this manner, the increase in bonding angle between the chip bonding pads 3 and the lead bonding regions 9 is mitigated or eliminated. Examples of the use of the corner rule for chip bonding configurations are provided in U.S. Pat. No. 5,923,092, the contents of which are incorporated herein by reference.
However, a bonding configuration in which the corner rule is applied results in an increased chip size if the bonding pad count is to be maintained. This is contrary to design integration, and contrary to manufacturing throughput in which an optimal “net die” count, or number of chips per wafer, is desired. Accordingly device fabrication costs are proportionally increased.